1. Field of the Invention
This invention concerns a semiconductor device used for mobile communication apparatus such as cellulars operation in a microwave band of 500 MHz to 2.5 GHz and, more in particular, it relates to a technique which is effective to high frequency powers amplifier of power-amplifying high frequency signals and outputting them.
2. Description of Related Art
In recent years, mobile communication apparatus typically represented by communication systems such as GSM (Global System for Mobile Communication), PCS (Personal Communication system), PDC (Personal Digital Cellular) system and CDMA (Code Division Multiple Access) system (so-called hand set telephone) have been Popularized world wide.
Generally, a mobile communication apparatus comprises an antenna for emitting and receiving electromagnetic waves, a high frequency power amplifier for amplifying high frequency signals under power modulation and supplying them to the antenna, a receiving section for processing high frequency signals received on the antenna, a control section for controlling them and a battery for supplying a power source voltage to them.
Such mobile communication apparatus and semiconductor devices used for the mobile communication apparatus have been disclosed, for example, in the known literatures described below.
(1) The constitution of the mobile communication apparatus is disclosed, for example, in xe2x80x9cHITACHI HYORONxe2x80x9d vol. 78, No. 11 (1996-11), pages 21 to 26 (Literature 1).
(2) Constitution of a typical high frequency power amplifier on the GSM system is described, for example, in ISSCC 98, DIGEST OF TECHNICAL PAPERS (Feb. 5, 1998), pages 50 to 55 (Literature 2).
According to the literatures, a threshold voltage of FET is controlled to an appropriate level for stable circuit design and decrease of leak current in an off state. In the constitution of the amplifier, two chips are arranged in parallel for final stage devices in a 3-stage amplifier circuit and synthesizing and an impedance-matching circuit is disposed to each of them for the synthesis of outputs of attain higher output than in the case of using one chip. The constitution of this amplifier is referred to as DD-DIMA technique (Divided Device and Collectively Impedance Matched Amplifier) in the literature.
(3) Amplifying devices applied to the high frequency power amplifiers are described, for example, in IEDM 97 Technical Digest (1997), pages 51 to 54 (Literature 3).
This literature discloses that an amplifier device is constituted with a power insulated gate type field effect transistor (hereinafter simply referred to as power MOSFET) using Si (silicon) semiconductors to attain high performance.
Specifically, the performance is improved by defining the gate length of a MOSFET to 0.4 xcexcm. Further, the drain breakdown voltage is set to 20 V or higher by disposing an offset layer of an about 0.7 xcexcm length on the side of the drain of the power MOSFET. Further, it is important to lower the gate resistance for high frequency operation and the gate resistance is decreased by a structure of short circuiting a metal silicide/silicon laminated gate electrode with an aluminum wiring (Al-shorted silicon gate structure).
(4) There has been a trend of adopting compound semiconductor (GaAs) wafers for making the device efficiency higher. Such a technical trend is described, for example, in NIKKEI ELECTRONICS 1998, 11, 2 (No. 729), pages 238 to 245 (Literature 4). However, as described also in this literature, the unit wafer cost in the GaAs technique is more expensive compared with Si.
For generalized use of the mobile communication apparatus, it has been demanded for further reduction of the size and weight, and decrease in the power consumption of the apparatus. For this purpose, it is necessary to attain further reduction in the size and weight and decrease in the power consumption for each of components constituting the mobile communication apparatus.
One of the components is a high frequency power amplifier for supplying high frequency signals to the antenna. Generally, the high frequency power amplifier most consumes electric power and it is effective of saving the consumption power of the mobile apparatus to decrease the consumption power of the high frequency power amplifier (improvement of efficiency).
In the GSM system amplifier using silicon (Si) semiconductors, it was attained an output voltage of about 3.5 W and a overall efficiency (xcex7all) of about 50% at a working frequency of 900 MHz and a power source voltage of 3.5 V. The overall efficiency is an efficiency in a high frequency power amplifier constituted with a three stage power amplifier of power MOSFET (high frequency module).
The performance of the power MOSFET using Si as the output stage amplifier device is about 55% power of a power-added efficiency (xcex7add) at 2 W output based on the DD-CIMA technique, and it was necessary to attain a power added efficiency of 65% or more in power MOSFET in order to improve the overall efficiency of the amplifier to 55% or more.
The power added efficiency (xcex7 add) in the microwave power MOSFET is defined, for example, in xe2x80x9cOptical Microwave Semiconductor Applied Technologyxe2x80x9d Feb. 29, 1996, first edition, first print (Published from Science Forum Co.), pages 59 to 66 (Literature 5).
Also in the PCS system amplifier, an output voltage of 2 W and an overall efficiency of 45% at a working frequency of 1900 MHz have been attained. The performance of the power MOSFET as the output stage amplifier device is about 50% at 1 W output. For improving the overall efficiency of the amplifier to 50% or more, it was necessary to attain the power-added efficiency of 55% or higher in the power MOSFET.
For improving the power-added efficiency of the amplifier device (power MOSFET), it is considered to decrease the on-resistance, gate resistance and parasitic capacitance and improvement of the mutual conductance.
It is an object of this invention to provide a technique capable of attaining a high power-added efficiency for a semiconductor device applied to a high frequency amplifier.
A specific object of this invention is to provide a technique capable of decreasing the on-resistance of a semiconductor device.
Another specific object of this invention is to provide a technique for improving the cut-off frequency.
A further object of this invention is to provide a semiconductor device capable of improving the power-added efficiency in high frequency and high power operation, as well as ensuring reliability and mass productivity together.
A still further object of this invention to provide a technique capable of reducing the size and the weight of a high frequency power amplifier.
Typical features of the invention disclosed in this patent application are to be explained briefly as below.
One of typical constitution of semiconductor devices according to this invention resides in a semiconductor device comprising:
a semiconductor substrate of a first conduction type,
a semiconductor layer of a first conduction type formed on the surface of the semiconductor substrate,
a first region and a second region of a second conduction type opposite to the first conduction type situated to a portion of a main surface of the semiconductor layer, being spaced apart from each other on both sides of a region to be formed with a channel, the second region comprising a low impurity concentration region in contact with the region to be formed with the channel and a high impurity concentration region in contact with the low impurity concentration region,
a gate electrode formed by way of a gate insulation film above the channel region,
a leach-through layer of a first conduction type formed to other portion of the main surface of the semiconductor layer so as to be in contact with the first region and the semiconductor substrate,
a first insulation film covering the gate electrode, the first region, the second region and the leach-through layer,
a first conductor plug, a second conductor plug and a third conductor plug connected, respectively, wish the first region, the high impurity concentration region of the second region and the leach-through layer by way of openings disposed in the first insulation film,
a first conductor layer connected with the first conductor plug and the third conductor plug and a second conductor layer connected with the second conductor plug, and
a third conductor layer connected with a lower surface of the semiconductor substrate.
According to the technical means described above, since conductor plugs are used for leading out electrodes for the first region (source), the high impurity concentration region of the second region (drain) and the leach-through layer (source punch-through layer), the first and the second conductor layers (first layer wiring M1) constitute an electrode pattern having a flat surface. Therefore, this can increase the degree of freedom for the arrangement of a backing wiring layer (second layer wiring M2) and M1xe2x80xa2M2 contact for realizing the wiring of lowered resistance to the first and second conductor layers.
Accordingly, the wiring resistance to the first region, the high impurity concentration region of the second region and the leach-through layer can be decreased. As a result, since the on-resistance can be decreased, this can contribute to the improvement for the power-added efficiency in the semiconductor device.
Another typical constitution for the semiconductor device of this invention is an insulated gate field effect semiconductor device having a P type semiconductor region and a drain offset region in contact with the P type semiconductor region, in which a gate electrode in contact with a gate insulation film is constituted with a P type semiconductor, and an N type layer is disposed on the surface of the P type semiconductor region.
By the constitution described above, since the gate electrode is constituted with a P type semiconductor, namely, constituted as a P type gate, a threshold voltage Vth is increased by 1 V in view of the difference of the work function. Therefore, a state of normally off, that is, an enhanced state can be maintained in a state of not giving a gate voltage irrespective of the disposition of the N type layer on the surface of the P type semiconductor region. Presence of the N type layer provides an effect of extending the extension of a depletion layer for the drain junction to improve the drain breakdown voltage. Then, when a P type gate device (P type gate MOSFET) having an identical aimed value for the drain breakdown voltage like that in the N type gate (P type gate power MOSFET) is designed, the impurity concentration in the drain offset region can be increased. This is because there is no more necessary to extend the depletion layer on the side of the drain offset region. Possibility of increasing the impurity concentration in the offset region means that the resistance in the drain offset region can be lowered compared with the N type gate device.
Further, presence of the N type layer can moderate the electric field on the surface of the channel region. Accordingly, the carrier mobility of the channel region can be improved. Improvement of the carrier mobility can be considered as a result of decreasing the resistive component in the relevant portion.
Further, improvement of the carrier mobility based on the constitution described above enables to shorten the gate length Lg and supply more electric current. Usually, as the gate length is shorter, carrier velocity is saturated remarkably making it difficult to supply a great amount of current.
As the result, when the on-resistance is compared between the P type gate device and the N type gate device under an identical breakdown voltage, it is possible to effectively decrease the resistance in the P type gate device than in the N type gate device. That is, P type gate power MOSFET can improve the power-added efficiency.